Implementation of 90 nm CMOS LFSR Test Vector Generator for FPGA Floating Point Arithmetic Unit

Abstract

In this paper, we present the LFSR Test Vector Generator for Floating Point Arithmetic Unit (FPAU); it improves the performance of multimedia processing with low hardware cost. Here, we focused on a decimal floating point unit which consists of adder and subtractor for high speed computing. It takes input as binary real numbers, converts them into single precision IEEE 754 format floating point numbers, performs operations and gives the output with high precision. We used Guard bit, Sticky bit and Round bit to get output with good precision. At last, we tested the unit by the values from LFSR. The FPAU was modeled and synthesized in Verilog HDL and LFSR was implemented 90nm CMOS technology